This invention relates generally to digital circuits, and more particularly, to methods and apparatus for resetting clock divider systems of digital circuits.
Clock divider systems are used in digital circuits to divide a master or xe2x80x9csystemxe2x80x9d clock into lower frequency clock signals. An idealized clock signal is a series of regularly occurring square wave pulses transitioning from a low (xe2x80x9cLOxe2x80x9d or xe2x80x9c0xe2x80x9d) state to a high (xe2x80x9cHIxe2x80x9dor xe2x80x9c1xe2x80x9d) state, and back to a LO state. Adjacent HI and LO states define a single cycle of the clock signal.
Digital circuits are typically triggered by the xe2x80x9cactivexe2x80x9d edge of a clock cycle. The active edge is often the rising edge of the square wave pulse, although it was sometimes alternatively the falling edge of the pulse. To operate properly, a digital circuit usually requires its various components to be synchronized with active edges of the clock cycles.
As noted, the function of a clock divider system is to take a master or xe2x80x9csystemxe2x80x9d clock and to divide it into lower frequencies (i.e., longer cycle) clock signals. Complex digital systems may use a fairly large number of such divided clock signals at various frequencies. However, since all of the clock signals are derived from the original system clock, they are all, in theory, all synchronized to the original system clock.
In FIG. 1, a clock divider 10 includes a number of flip-flops 12 which are connected as a xe2x80x9cripple-typexe2x80x9d counter. More particularly, the clock divider 10 includes a number of xe2x80x9cDxe2x80x9d type flip-flops, where a Q* (Q Bar) output of the flip-flop is coupled to a D input of the flip-flop. The first flip-flop 12 has its clock input C coupled to the system (or other) clock xe2x80x9cclkxe2x80x9d and has its Q output coupled to the clock input C of the next flip-flop 12 in the line. The Q output of the last flip-flop 12 is the divided output 14 of the clock divider 10.
With the ripple-type clock divider of FIG. 1, the Q output of each of the flip-flops 12 is one-half the frequency of its input clock. Therefore, the Q output of the first flip-flop 12 is one-half of that of the system clock, the Q output of the second flip-flop 12 is one quarter of that of the system clock, and the output of the nth flip-flop 12 is xc2xdn of that of the system clock.
As will be discussed in greater detail subsequently, there are times when it is necessary to deterministically know the state of each of the flip-flops in the clock divider 10. For this reason, a reset (R) input is provided to reset all of the flip-flops 12 to a known state. Typically, this known state is Q=0 and, of course, Q*=1, although in other types of flip-flops a reset may set Q to 1 and Q*to 0. This reset signal can be derived from a number of sources. For example, a reset signal on a line 16 can come from a signal applied to a system reset pin 18 via system reset logic 19, a test reset pin 20, or JTAG pins 22 via JTAG logic 24. These pins 18, 20, and collectively 22 are all typically external pins of an integrated circuit package. The JTAG pins 22 are coupled to JTAG logic 24, which, among other things, can provide a reset. signal on line 16.
The problem with ripple-type clock dividers such as clock divider 10 of FIG. 1, is that the divided output signal 14 is not precisely synchronized with the system clock. This is because each of the flip-flops 12 develop a slight time delay, which means that the active edge of its output signal is phase-shifted from the active edge of the system clock. Since this problem increases with each additional flip-flop or xe2x80x9cstagexe2x80x9d of the clock divider 10, ripple-type clock dividers tend not to be used unless the divider has only one or two stages.
A more versatile clock divider system 26 is illustrated in FIG. 2. This clock divider 26 is a divide-by-N type divider, with a one-clock-width high time. The advantage of the divide-by-N counter is that the divided output 28 is a clock having active edges that are well synchronized with that of the system clock clk. The divider 26 includes a counter 30, a decoder 32, and a flip-flop 34. To divide, for example, by 8, the number 7 (111 in binary) is loaded into the counter 30, and then the counter 30 counts down to zero. When the decoder 32 determines that the count of the counter 30 has reached zero, an output on a line 35 changes state to simultaneously prepare the counter 30 to reload the number 7 (i.e., Q1=Q2=Q3=1) into the counter 30 and to change the state at the D input of flip-flop 34. The signal on line 35 is re-synchronized with the system clock via the clock input C of flip-flop 34 to provide a synchronous clock signal on line 28 which is one-eighth of the frequency of the system clock. Other frequency divisions are possible by loading other numbers into the counter 30. Since the clock divider 26 also must be reset to a deterministic state for various purposes, a reset line 36 may be coupled to the system reset pin 18 via system reset logic 19, the test reset pin 20, and/or the JTAG pins 22 via JTAG logic 24.
It should be noted that there are a great many types of clock divider circuits in addition to those illustrated by FIGS. 1 and 2. For example, there are clock divider circuits which divide a system clock by a fractional number, and divider implementations which use other flip flop types, such as toggle flip flops and JK flip flops. However, as noted previously, there are times when the state of the clock divider, no matter what type, must be known, requiring a methodology for deterministically resetting the clock dividers.
One of those times that it is imperative to know the starting states of a clock divider system is during the testing of integrated circuits as part of the manufacturing process. Realistically, complex digital integrated circuits cannot be manufactured without extensive operability testing. This is because the manufacture of integrated circuits is imperfect and even one defective gate or transistor can ruin the reliability or even the functionality of the chip.
Digital integrated circuit chips are typically tested by test programs containing what is known as xe2x80x9ctest vectorsxe2x80x9d. Test vectors are a string of bits containing input stimulus bits (to be applied to input pins) and output checking bits (to be compared with the output pins). For each of the test vectors, the program applies the input stimulus bit values to the input pins and checks the output pins against the output checking bit values for each xcex94T, comparing the actual outputs with the predicted output values based upon the desired functionality of the integrated circuit.
The problem with this scenario is that it is necessary to know the state of the internal memory-type devices, (such as the flip-flops, counters, registers, etc.), of the integrated circuit before the test vectors can be successfully applied to the circuits. Since on xe2x80x9cstart upxe2x80x9d, the contents of such memory-type devices are essentially random, most chip designers provide an external test reset pin or JTAG pins to reset memory-type devices of the system to a known state. As is well known to those skilled in the art, in addition to resetting memory-type devices, JTAG functionality allows for a great deal of testing of integrated circuits and their interconnections, permitting xe2x80x9cboundary scanxe2x80x9d tests, etc.
The problem with adding a pin 20 just to reset the clock dividers is that it adds another pin to the integrated circuit package. However, each additional pin comes at a significant economic cost. For example, an additional pin may require a larger IC package, which can be considerably more expensive than a lower pin-count package. Furthermore, adding another pin adds another bit to the test vectors which, in theory, can double the amount of test vectors that must be generated to fully test the chip. Since there is an appreciable cost associated with the use of test equipment, the extra pin therefore adds to the complexity and expense of testing the chip.
The present invention provides a method and apparatus for providing deterministic resets for clock divider systems and the like. The invention does not require the use of an additional, external test reset pin, and as a consequence, saves on pin count, on testing complexity, and possibly on integrated circuit package size.
Briefly, a clock divider system with reset synchronization includes a divider circuit, a synchronizer circuit, and a synchronous delay circuit. The clock divider circuit has a clock input, a divider reset input, and a divided clock output which is at a lower frequency than that at the clock input. The synchronizer circuit has a clock input and an asynchronous reset input, and synchronized reset output having an active edge aligned with an active edge of the clock. The asynchronous delay circuit has a clock input and a synchronized reset input coupled to the synchronized reset output of the synchronizer, and an output coupled to the divider reset input of the divider.
A method for providing reset synchronization for a clock divider system includes the operations of receiving an asynchronous reset signal, developing a reset synchronization signal aligned with an active edge of a clock, delaying the reset synchronization signal for at least one cycle to provide a delayed reset synchronization signal, and developing a clock divider reset signal from the delayed reset synchronization signal which is aligned with an active edge of the clock. Preferably, the operation of developing a reset synchronization signal includes first developing a pre-reset synchronization signal aligned with the next active edge of the clock, and developing the reset synchronization signal from the preset synchronization signal in alignment with the next active edge of the clock. Other methods of synchronization besides the dual rank synchronizer method are possible.
The present invention therefore uses an already existing asynchronous system reset signal to produce a test reset signal which deterministically resets the divide-by-N clock divider circuits. The requirement for a separate, external test reset pin has therefore been eliminated. This reduces the complexity of the integrated circuit, reduces the complexity and cost of testing the integrated circuit, and consequently reduces the cost of the integrated circuit.
These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following descriptions of the invention and a study of the several figures of the drawing.